QFN segmented stencil

QFN Footprints to prevent Float

The QFN (quad flat pack, no leads) package has long been the staple of the small PC board. In fact, with the wafer scale BGA, it’s one of the more common packages for new chip designs and is my package of choice for my microcontroller designs. It took me a while to make that leap, but that’s where I go, and the smaller the better. 0.4 mm pitch is just fine with me.

One of the challenges presented by the QFN in it’s early days was the large exposed pad in the center. Not all QFNs come with an exposed metal pad underneath, but many do, and that can still cause problems with reflow solder. The pad itself isn’t the problem, but improper solder paste stencil layer design can be.

The problem comes in due to the fact that the center pad often covers a substantial portion of the underside surface area while the signal pads are very small. This difference in aspect ration can cause a disproportionally larger amount of solder in the middle than on the pads. The solder in the middle will bulge up, lifting the QFN up a bit so that some of the signal pads are too high to reach the solder on theri pads.

The default stencil layer in the CAD library footprint might have an opening the full size of the metal pad. If that’s the case, you’ll need to modify the footprint so that you get 50 to 75% coverage with solder paste. If you don’t, you may very well have yield problems due to float.

Avoiding QFN Float

The following illustration shows a stencil with too large an opening for the center pad (stencil on the left), a segmented paste layer in the CAD footprint (image center), and a segmented stencil (on the right):

QFN Stencil patterns

You may note that I said to shoot for 50 to 75% coverage and ask: “Well, is it 50% or 75%? What gives?”

I do acknowledge that I have given you a bit of ambiguity. However, anything in that range should be fine for prototype boards. If you’re going for volume production, you’ll want to work with your contract manufacturer to optimize the design for best high volume yield.

Good news on this front is that many QFN manufacturers and parts library creators have taken notice of this. It’s far more likely now, than it was ten years ago, to find a datasheet correctly illustrating this, and CAD footprints created correctly. But, always check your footprints to make sure.

When you’ve verified your design, including the solder stencil layer, head to www.screamingcircuits.com to quote and order online.

Duane Benson